1. Field of the Invention
The invention relates to a dynamic random access memory (hereinafter referred to DRAM). More particularly, it relates to a layout structure of the DRAM using capacitor elements with a ferroelectric film.
2. Description of the Related Art
Conventionally, a DRAM comprising a memory cell in which one transistor element and one capacitor element are combined is known as a semiconductor memory device having high integration. The capacitor element applied for this conventional DRAM has been mainly formed of a capacitor made of an insulating film such as SiO.sub.2 and SiN.
However, since such an insulating film has a relatively low relative dielectric constant (.epsilon.) (SiO.sub.2 :(.epsilon.)=3.9; SiN:(.epsilon.)=7.8), it is necessary to reduce a thickness of the film to a certain level in the limited cell size for having higher integration. For example, in order to obtain integration of the level of 64 Mbit, the film thickness has to be reduced to about 50 angstroms. It is difficult to manufacture such a thin insulating film by the present state of art with sufficient reliability.
It has also been conventional to form a DRAM in which a ferroelectric film such as PZT and PLZT is used instead of the insulating film described above for the capacitor. In such a DRAM, since the ferroelectric film has a high relative dielectric constant (.epsilon.=about 500-1000), the capacitor element formation area can be reduced and the limitation of the film thickness can be relaxed.
A conventional type DRAM having a layout structure as shown in FIG. 5 (folded bit line type) has been proposed. In this Figure, the reference numeral 1 designates a bit contact formation region, 2 designates a capacitor element formation area especially showing capacitor electrode pattern, 3 designates a word line, 4 designates an active region and G designate a gate, respectively.
As described above, the conventional ferroelectric type DRAM has the a layout structure of DRAM cell units A each of which comprises a pair of DRAM in which ferroelectric type capacitors are disposed through the intermediary of respective transistors on the right and left side in the bit contact formation region and are arranged in X-Y direction.
However, such a conventional type DRAM has a drawback as to integration of the device because a constant distance (a) is kept between the DRAM cell units arranged in the direction of X as shown in FIG. 5.
In addition, it is a problem that the density of placement of the bit contact and capacitor element 2 in the DRAM cell unit A arranged in the direction Y is partially great and partially small, respectively.